TigerSHARC
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| Designer | Analog Devices |
|---|---|
| Bits | 32-bit |
| Introduced | 2000 |
| Design | DSP/RISC |
| Type | Load–store |
| Encoding | ? |
| Branching | ? |
| Endianness | ? |
| Registers | |
| 2 × 32 × 32-bit address registers | |
| General-purpose | 2 × 32 × 32-bit registers (addressable in 16-bit parts) |
TigerSHARC refers to a family of microprocessors currently manufactured by Analog Devices Inc (ADI). It is superscalar and features data-parallelism in the form of short-vector SIMD and subword (16-bit) parallelism (SWAR). It consists of:[1]
- Two separate computation blocks (CompBlocks) each with 32 general-purpose registers and their own ALU, multiplier, and shifter; 256-bit read and 128-bit write bus access
- Two integer ALUs (JALU, KALU) each with 32 registers; mainly intended for address generation, but is also capable of general integer arithmetic; 32-bit data bus
- A sequencer with 128-entry 4-way associative branch target buffer; 128-bit data bus
- Three separate internal memory banks (SRAM)
- External port with DMA
See also
[edit]References
[edit]- ↑ Fridman, Jose; Greenfield, Zvi (2000). "THE TIGERSHARC DSP ARCHITECTURE" (PDF).
External links
[edit]
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