Talk:UltraSPARC T2
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Any references where the pipeline stage information came from? Thread selection should probably be before fetch. But the way it's shown is still possible, just not the most straight forward to implement.
- The way it is currently listed matches up with diagrams in the article "Niagara 2 Opens the Floodgates" from the Nov 2006 issue of Microprocessor Report. This is also confirmed in a presentation given at the Fall Microprocessor Forum 2006 by Robert Golla of Sun Microsystems entitled "Niagara2: A Highly Threaded Server-on-a-Chip".--141.212.106.126 19:45, 9 April 2007 (UTC)
The section "Performance improvement versus T1" should be altered. Maybe the 78.5/62.3 SPECintRate/SPECfpRate were single-chip-records when the UltraSPARC T2 was released, but with the Nehalem out a new record-holder is on the market: Intel Core i7-965 EE 126/99.1 SPECintRate/SPECfpRate. —Preceding unsigned comment added by 84.191.254.61 (talk) 12:43, 2 November 2009 (UTC)
Cache memory: What I remember regarding T1 chips' performance problems was the FPU weakness, and another bit is hinted at by the change in ALU:Threads ratio. What I hadn't known about was the L2 cache size: It seems they killed the whole product by cheaping out on L2 cache (4MB)! — Preceding unsigned comment added by 188.174.56.168 (talk) 17:31, 17 March 2025 (UTC)