Talk:I.MX

Code names

The IMx 25 products seem to have a code name of Senna. Is there some list of names for these parts. 216.94.244.169 (talk) 20:58, 28 June 2011 (UTC)

External links modified

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• Added archive https://web.archive.org/web/20160304040324/http://www.nxp.com/files/training/doc/dwf/DWF13_APF_CON_T0838.pdf to http://www.nxp.com/files/training/doc/dwf/DWF13_APF_CON_T0838.pdf
• Added archive https://web.archive.org/web/20110607122239/http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIMX51EREADEVSYS&aspll=1 to http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RDIMX51EREADEVSYS&aspll=1

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i.mx61 UL

The page is missing a section about the "Ultra Light" series, unlike the regular imx.61, the i.mx61-UL are based on cortex A7, not A9. — Preceding unsigned comment added by Chgans (talk • contribs) 22:44, 5 October 2017 (UTC)

MX-1 image

I moved the image link over from Freescale DragonBall, see Talk:Freescale DragonBall#MX-1 image Tomdo08 (talk) 00:25, 22 January 2018 (UTC)

NPOV

i flagged this article for NPOV because several sections use excerpts from the manufacturer's website which are full of marketing language — Preceding unsigned comment added by Flufkity (talk • contribs) 16:59, 2 October 2018 (UTC)

Can you clarify which exact sections are "excerpts ... full of marketing language"? We might be able to remove/improve those.

Although I wasn't the one to flag this article for NPOV, there is marketing language in several sections. Here are some examples: "Fast multi-OS platform deployment …", "Deploy rich, fully independent graphics content…", "Rapidly deploy multiple products …", and "Fully supported on NXP’s 10 and 15-year Longevity Program". Any content that cites as its reference a vendor link is suspect. Gregmg

Arm Cortex M processors are not "Realtime processors"

This article repeatedly describes the Cortex M processors (M4, M7, etc.) as real time processors , which they are not. Arm makes the Cortex R series for real time, cycle accurate processing. The Cortex M are nearly real time, but the interrupt controller introduces cycle count errors. Also affecting real time processing is the use of level 1 code and data cache memories for most Cortex M processors. Finally, specific to the Cortex M7, the processor has a dual issue instruction pipeline that greatly varies execution times of code from one pass to another.

This should be changed in this article as it does not correctly represent the parts being discussed. ~2026-34819-07 (talk) 06:07, 14 June 2026 (UTC)

Thank you for noticing. Will do. 海盐沙冰 _{/ aka irisChronomia / Talk} 07:41, 14 June 2026 (UTC)