Talk:Dynamic random-access memory

Removed eDRAM section

I removed this section for a number of reasons. First, historically EDRAM means something very different; usually hybrid chips that use SRAM cells to help decrease the latency of an SDRAM module. Second, after several minutes of searching online I can only find a few references to NEC's eDRAM, all of which lack details and have popped up within the last few days. The articles that do contain details describe eDRAM as a separate LSI chip to be used as high bandwidth video-related RAM (presumably for texture storage), not integrated with the XBox 2's PPC970-derivative CPU (which is designed by IBM anyway). Furthermore, the Playstation 2 uses Rambus RDRAM, the Game Cube doesn't even use DRAM for the main system memory (uses SRAM), and all that is known about the Playstation 3's memory technology is that it will use the Rambus interface. Please cite some sources for your information, since I cannot find anything to support the section, but can find plenty of counter-examples. -- uberpenguin 00:50, 2005 May 3 (UTC)

Suggestion to refer also the RLDRAM

I suggest to mention and refer RLDRAM similary to the mentioning of the other DRAM types. User:elcha, 08 October 2006

Looks like RLDRAM is just a low(-er) latency SDRAM. It seems to me that it's more a brand name than an actual novel DRAM arrangement. -- mattb @ 2006-10-08T16:08Z

SLDRAM

Found this memory being mentioned in a IT magazine edited in October 1997.

According to the article, a consortium called Sync-Link or SLDRAM (made by Mitsubishi, NEC and Siemens) was established to compete against Intel-Rambus.

Memory chips were supposed to appear the next year (1998) and were following the concepts Rambus. As Direct RDRAM, SLDRAM would have worked on a 16bit bus at a high frequency. The consortium estimated the performances would be comparable to SDRAM while some members estimated 3.2GB/s by interconnecting several independent SLDRAM subsystems.

The article mentions two websites as further reference SciZZL and SLDRAM, the later is currently just a parked domain. I don't know if the memory chips were in the end actually made.

If anyone is interested in a copy of the article, I can scan the page from the magazine and publish it somewhere.

About burst length and latencies

I would like to enlight you about DRAM and RAM burst length. First of all usual RAS (from row to row activation) latency is about 40-80 ns or 1/(40*10^(-9)) = 25,000,000 Hz or 25 MHz, 80 ns latency is equal to 12.5 MHz frequency. CAS latency (from column to column latency) usualy for DDR2-DDR5 is 9-15 ns or 111 MHz for 9 ns DRAM and 66.66 MHz for 15 ns DRAM. CAS latency in nanoseconds can be calculated by dividing real DRAM frequency by CAS latency cycles. For example DDR5-6400 have real frequency 3200 MHz and if CL is 30 cycles, then efective DDR5-6400 RAM speed on Randome RAM locations accesses is 3200/30 = 106.66 MHz. Or 1/(106.66666 * 10^6) = 9.375* 10^(-9) s = 9.4 ns. For short explanation how RAM working. RAM divided into rows and columns with ROW and Column selection from RAM address decoders. First selected one ROW of RAM. Then from that RAM row bits cells floating bits 0s or 1s. If RAM made with 4096 Rows and 1024 columns, then during selection one of 4096 Rows all bits charge from 1024 columns begin to move to 1024 amplifers. This 1024 amplifers can amplify and latch (put those bits in SRAM cells) those bits. Then depending on each drained charge from column value (0 or 1), amplified charge returned to each column and sealed perhaps by turning of ROW line (this explained on this page). This amplification possibly is reason why DRAM latencies are so big and it is so slow. To refresh DRAM just need to refresh 4096 Rows and this will refresh 4096*1024 = 4,194,304 bits or 4 Megabits. In this https://www.mouser.com/datasheet/2/671/64mb_x4x8x16_sdram-1282423.pdf 1999 year datasheet described 64 Megabit chip in 3 possible variants (4 bits data bus, 8 bits data bus and 16 bits data bus). There is 4 banks in any of this chip. Means that there is 4 banks (4 devices or grids) of size 4096(rows)*1024(columns) for example. This 64 Mbit RAM chip can be programed to function in burst length 1, 2, 4, 8 or full page. Page mean number of columns assigned to one ROW. So in 4096 rows times 1024 columns, one page is 1024 columns and all 1024 bits from each column can be latched to SRAM cells and then very fast transmited through 64 bits data bus to CPU. When program code jumping through RAM addresses, then such burst lenght become almost useless and maybe can works slower than burst length 8. That's why there is options. Normally device functioning by reading from 8 RAM addresses of same ROW at once and then jumping to RAM address (Current RAM address)+8 at burst length of 8. This is very useful for big data transfers (but better then use all page burst length). DDR4 seems have burst length of 8 and probably full page burst length and DDR5 seems have burst length 16, but those 2 channels can mean actually the same like burst length 8 for DDR4, just more flexible. GDDR5, GDDR6, GDDR6X seems have burst lenght 16 or 32 and probably also have full page burst length and textures can be transfered to CPU very fast, almost instantly across about 20 GHz signals if this speed and frequency coding and deconding is real, but even 4 GHz transmition through conventional bus should suffice enough for GPU. For example if GDDR CAS frequency is 100 MHz and burst length 32, then speed will be like 3.2 GHz bus. And if burst length is full page of size 8192 then data bus effective frequency on GDDR RAM can grow to about 100-1000 GHz and still to get usefullnes of RAM full pages bursts. GDDR5 or GDDR6 chips have seems 16 banks so that there would be shorter columns and charge of bit cell wouldn't be lost when moving across RAM one bank columns of selected ROW. Also RAM refreshing probably can be done on all 16 banks at same time, which is faster than on larger grid banks of number of 4. ~2026-40634-39 (talk) 17:52, 25 July 2026 (UTC)

Aside from attempting to "enlight(en)" us, what exactly are you proposing? You've only provided a reference to a datasheet. That's interesting, but in a vacuum of other reliable sources, I'm not sure what the point of this narrative is. Are you suggesting a change to the article? An addition? A clarification? cheers, anastrophe, an editor he is. 21:49, 25 July 2026 (UTC)