Open JTAG
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| Open JTAG | |
|---|---|
| Original author | Ruben Mileca |
| Written in | VHDL |
| License | LGPL |
| Website | www |
| Repository | opencores |
The Open JTAG project is an open source project released under GNU License.
It is a complete hardware and software JTAG reference design, based on a simple hardware composed by a FTDI FT245 USB front-end and an Altera EPM570 MAX II CPLD. The capabilities of this hardware configuration make the Open JTAG device able to output TCK signals at 24 MHz using macro-instructions sent from the host end.
The scope is to give the community a JTAG device not based on the PC parallel port: Open JTAG uses the USB channel to communicate with the internal CPLD, sending macro-instructions as fast as possible. The complete project (Beta version) is available at OpenCores.org[1] and the Open JTAG project official site.[2]
References
[edit]- ↑ OpenCores Open JTAG project
- ↑ "Open JTAG official site". Archived from the original on 2010-07-03. Retrieved 2010-07-26.
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