MVAPICH

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MVAPICH

Stable release	3.0 / February 16, 2024; 2 years ago (2024-02-16)

Operating system	Unix, Linux
Type	Library
License	New BSD License (free software)
Website	mvapich.cse.ohio-state.edu,mug.mvapich.cse.ohio-state.edu

MVAPICH, also known as MVAPICH2, is a BSD-licensed implementation of the MPI standard developed by Ohio State University.^[1]^[2] MVAPICH comes in a number of flavors:^[3]

MVAPICH2 ("renamed" as "MVAPICH" with the 3.0 releases^[4]), with support for InfiniBand, iWARP, RoCE, and Intel Omni-Path
MVAPICH2-X, with support for PGAS and OpenSHMEM
MVAPICH2-GDR, with support for InfiniBand and NVIDIA and AMD GPUs ^[5]
MVAPICH-PLUS, an enhanced fusing of MVAPICH2-X and MVAPICH2-GDR beginning its releases in 2023/24 with the 3.0 series.
MVAPICH2-MIC, with support for InfiniBand and Intel MIC
MVAPICH2-Virt, with support for InfiniBand and SR-IOV
MVAPICH2-EA, which is energy-aware and supports InfiniBand, iWARP, and RoCE

References

[edit]

↑ "MVAPICH Home". Retrieved 2021-04-14.
↑ "MVAPICH at NVIDIA Developer". May 2012. Retrieved 28 March 2016.
↑ "MVAPICH :: Overview". Retrieved 2024-05-17.
↑ "MVAPICH 3.0 release changelog". Retrieved 2024-05-17.
↑ "MVAPICH2-GDR 2.3.7 Changelog". Retrieved 2024-05-17.

External links

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v t e Parallel computing
General	Distributed computing Parallel computing Parallel algorithm Massively parallel Cloud computing High-performance computing Multiprocessing Manycore processor GPGPU Computer network Systolic array
Levels	Bit Instruction Thread Task Data Memory Loop Pipeline
Multithreading	Temporal Simultaneous (SMT) Simultaneous and heterogenous Speculative (SpMT) Preemptive Cooperative Clustered multi-thread (CMT) Hardware scout
Theory	PRAM model PEM model Analysis of parallel algorithms Amdahl's law Gustafson's law Cost efficiency Karp–Flatt metric Slowdown Speedup
Elements	Process Thread Fiber Instruction window Array
Coordination	Multiprocessing Memory coherence Cache coherence Cache invalidation Barrier Synchronization Application checkpointing
Programming	Stream processing Dataflow programming Models Implicit parallelism Explicit parallelism Concurrency Non-blocking algorithm
Hardware	Flynn's taxonomy SISD SIMD Array processing (SIMT) Pipelined processing Associative processing MISD MIMD Dataflow architecture Pipelined processor Superscalar processor Vector processor Multiprocessor symmetric asymmetric Memory shared distributed distributed shared UMA NUMA COMA Massively parallel computer Computer cluster Beowulf cluster Grid computer Hardware acceleration
APIs	Ateji PX Boost Chapel HPX Charm++ Cilk Coarray Fortran CUDA Dryad C++ AMP Global Arrays GPUOpen MPI OpenMP OpenCL OpenHMPP OpenACC Parallel Extensions PVM pthreads RaftLib ROCm UPC TBB ZPL
Problems	Automatic parallelization Cache stampede Deadlock Deterministic algorithm Embarrassingly parallel Parallel slowdown Race condition Software lockout Scalability Starvation
Category: Parallel computing

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