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JESD204B is a revision of the JEDEC standard Serial Interface for Data Converters (document number JESD204), which connects data converters (analog-to-digital converters and digital-to-analog converters) to logic devices such as FPGAs, ASICs and DSPs over a high-speed serial link.[1] JESD204B, the second revision, appeared in July 2011.[2] It raises the maximum lane rate to 12.5 Gbit/s and adds deterministic, repeatable latency across the link.[3]
Background and revisions
[edit]JESD204 needs fewer interconnects between converter and logic device than parallel CMOS or LVDS interfaces, which simplifies printed circuit board layout.[1] The revisions up to B are:
- JESD204 (2006): one lane, one converter, up to 3.125 Gbit/s.
- JESD204A (2008): multiple lanes and converters, up to 3.125 Gbit/s.
- JESD204B (2011): up to 12.5 Gbit/s per lane, deterministic latency, device subclasses, and a common device clock distributed to all devices, from which each derives its frame and multiframe clocks.[2]
JESD204C (2017) raised the lane rate to 32.45 Gbit/s and added 64b/66b and 64b/80b link layers. It does not replace JESD204B. It stays backward compatible and retains the 8b/10b link layer as a normative option alongside the newer encodings.[3]
Technical characteristics
[edit]The link is a point-to-point serial connection over differential lanes driven with current-mode logic (CML), the signalling used by the multi-gigabit transceivers (SerDes) in FPGAs and ASICs. 8b/10b encoding embeds the clock in the data stream, so no separate clock line is needed, and the payload may optionally be scrambled.[1] A link uses up to 32 lanes.
Functionality spans three layers. A transport layer maps converter samples into frames, a data link layer handles encoding, synchronisation and lane alignment, and a physical layer (PHY) drives the serial lanes. A link is defined by parameters including the number of lanes (L), converters (M), octets per frame (F), samples per converter per frame (S), converter resolution (N), word width (N′) and frames per multiframe (K).[2] At startup the lanes are aligned by the Initial Lane Alignment Sequence (ILAS) using defined 8b/10b control characters.[1]
Frame structure and lane rate
[edit]Converter samples are organised into a nested structure of octets, frames and multiframes. An octet is 8 bits. A sample word of N′ bits carries the converter's N bits plus optional control and tail bits, and N′ is normally padded to a multiple of 4 bits (a nibble) rather than a full octet, so a 12 bit converter can use N′ = 12. A frame is F octets per lane spanning one frame clock period and carrying S samples per converter. A multiframe is K frames and forms the unit for alignment and timing. Its boundary comes from the local multiframe clock, which SYSREF (or SYNC~) resets for deterministic latency.[2]
The lane rate follows from these parameters and the 8b/10b overhead.
where M is the number of converters, N′ the bits per sample, fs the sample rate and L the number of lanes, the factor 10/8 covering 8b/10b line coding. For example, a converter device with four 14 bit converters (N′ = 16), each at 500 MSPS, over eight lanes needs 5 Gbit/s per lane.[4]
Deterministic latency and subclasses
[edit]Unlike its predecessors, JESD204B keeps interface latency repeatable across power cycles and re-synchronisations.[5] It introduces the SYSREF signal as a timing reference that aligns the per-device clock dividers, the local multiframe clock. Three device subclasses are defined:[2][5]
- Subclass 0: no deterministic latency, equivalent to JESD204A.
- Subclass 1: deterministic latency via SYSREF.
- Subclass 2: deterministic latency via SYNC~.
Subclasses 1 and 2 reach the same deterministic latency by different signals, differing in the usable device-clock range rather than in achievable precision.[2] An informative annex of the standard recommends a Subclass 1 (SYSREF) approach for device-clock rates above about 500 MHz.[6]
Deterministic latency matters where downstream processing needs a fixed time-of-flight from the analogue front end, or where multiple converter devices must be sample-aligned, as in multi-channel and beamforming receivers.[7]
Applications
[edit]The interface is used mainly in high-throughput systems such as wireless communications, radar, test and measurement, and medical imaging.[1]
References
[edit]- 1 2 3 4 5 Harris, Jonathan (2013). JESD204B Survival Guide (PDF) (Technical report). Analog Devices. Retrieved 2026-07-01.
- 1 2 3 4 5 6 JEDEC Solid State Technology Association (July 2011). JESD204B: Serial Interface for Data Converters (Technical report). JEDEC. JESD204B.
- 1 2 Texas Instruments (2020). What to Know About the Differences Between JESD204B and JESD204C (Technical report). SBAA517. Retrieved 2026-07-01.
- ↑ "JESD204 documentation (Lane rate math)". Retrieved 2026-07-01.
- 1 2 Beavers, Ian (2014). Demystifying Deterministic Latency Within JESD204B Converters (Technical report). Analog Devices. MS-2626. Retrieved 2026-07-01.
- ↑ JEDEC Solid State Technology Association (July 2011). JESD204B: Serial Interface for Data Converters (Technical report). JEDEC. Annex B (informative). JESD204B.
- ↑ Bellato, M.; et al. (2017). "A JESD204B-Compliant Architecture for Remote and Deterministic-Latency Operation". IEEE Transactions on Nuclear Science. doi:10.1109/TNS.2017.2655569.