Talk:Zen 6

No mention of the “sea of wires”?

This seems to be the key new thing for Zen 6, so it should be mentioned.
For anyone who doesn’t know: Basically, the current interconnect between cores is similar to a network interface, and has to serialize and de-serialize the data. Which is a massive bottleneck. The “sea of wires” is the concept of putting a layer below the CPU that can just connect everything to everything. Something that was previously simply too overwhelmingly complex to do, but can now be done. This represents a massive performance increase (for everything that uses multiple cores, especially if it overwhelms the caches), and is much closer to an ideal situation. (Stacking the cores would be even better due to shorter pathways, but it seems putting micro- (heat/regular) pipes in-between everything to get it cooled is more complicated than one might think.) ~2026-24869-22 (talk) 08:19, 23 April 2026 (UTC)

Zen 6 is officially announced for server / enterprise

On 23. July 2026, AMD has officially announced Zen 6 for their Epyc lineup. AMD's official page with a list of announced CPUs is here. Both the 32-core Zen 6c CCD and the 12-core Zen 6 CCD use TSMC 2nm process node. (Of course they didn't say anything about mobile variants, those might very well use 3nm manufacturing.) Not sure what node IODs use, but one big change there is: There will be 2 IODs per socket instead of 1, unlike Zen 2 to 5. (Also, I don't think AMD explicitly announced this, but based on pictures on AMDs page, they designed 2 different IODs. Socket SP7 looks to be using a different IOD than CPUs on SP8, this would mean that each IOD on SP7 implements 8 DDR5 channel, while each SP8 IOD implements only 4 DDR5 channels.)

A few other things:

• Both Zen 6c and Zen 6 CCD use 4MiB L3 cache per core. So the 32-core Zen 6c CCD has 128MiB L3 cache and the 12-core Zen 6 CCD has 48MiB L3 cache.
• The stacked 3D V-Cache is now 96 MiB, up from 64 MiB. Combined with the 48MiB cache on the CCD itself, each 12-core group can use up to 144MiB L3 cache.
• I don't know what Wikipedia's policy on this is, AMD said Epyc 9006 SP7 should be generally available starting from Q4 2026, but large cloud providers like Azure and others will start on-boarding Zen 6 in the coming month, long before Q4. Which date do Wikipedia usually use?
• The article currently has a lot of information based on rumors and speculations. Now that Zen 6 is officially announced, should those rumors and speculations be removed?

~2026-42051-52 (talk) 09:27, 28 July 2026 (UTC)

I suggest you reread the page you linked to, it is quite easy to let your preconceptions run away and reach an incorrect conclusion.

There are several mentions of "9006 SP7" and "9006 SP8", but not once do the strings "Socket SP7" or "Socket SP8" occur. You might think "SP7" and "SP8" refer to new sockets, but not once is that explicitly stated. I don't know whether they're deliberately trying to confuse people or someone accidentally used a shorthand too close to another shorthand.

To my knowledge neither DDR6 nor PCIe 6.0 are ready for production. I would expect a new socket with the next generation to support those, but I suspect this generation will continue with Socket SP6. Unless a better reference is available I think sTR6, SP7 and SP8 should be left off as speculation right now. ~2026-50336-16 (talk) 02:38, 18 September 2026 (UTC)

Looking further there are numerous mentions of "SP7 platform" and "SP8 platform", but no absolute statements about those. There are also "hints" of a socket sTR6, but nowhere are those declared confirmed. All of those are rumors or suspicions not facts. Please point to a source which doesn't include weasel words. ~2026-51069-74 (talk) 02:41, 22 September 2026 (UTC)

I have started adding CPU product tables.

However I noticed that the CPU's AMD has publicly announced have inconstancies. Many EPYC CPUs do not have matching total cores =/= total cache. Cache x CCD = total cache and cores x CCD = total cores do not match on most of them.

I have added CPU's which do have matching total cores =/= total cache. DrWhatNoName (talk) 19:56, 23 September 2026 (UTC)