// Workers AI · dad joke modeWhat did dual-ported RAM say? I'm open to access.

Dual-ported RAM (DPRAM), also called dual-port RAM, is a type of random-access memory (RAM) that can be accessed via two different buses.

A simple dual-port RAM (usually called two-port RAM or 1R1W RAM) allows only read access through one of the ports and write access through the other, in which case the same memory location cannot be accessed simultaneously through the ports since a write operation modifies the data and therefore needs to be synchronized with a read or another write operation.

A dual-port RAM may be built from single-port memory cells to reduce cost or circuit complexity, and the performance penalty associated with it, which may still allow simultaneous read and write accesses to different memory locations depending on the partitioning of the memory array and having duplicate decoder paths to the partitions.

A true dual-port memory has two independent ports, which means that the memory array is built from dual-port memory-cells, and the address, data, and control lines of the two ports are connected to dedicated IO controllers so that the same memory location can be read through the ports simultaneously. A write operation through one of the ports still needs to be synchronized with a read or write operation to the same memory location through the other port.

Examples

Video RAM (VRAM) is a common form of dual-ported dynamic RAM mostly used for video memory, allowing the central processing unit (CPU) to draw the image at the same time the video hardware is reading it out to the screen.

Apart from VRAM, most other types of dual-ported RAM are based on static RAM technology.

Most CPUs implement the processor registers as a small dual-ported or multi-ported RAM.

Multi-port SRAM structure

A typical SRAM bit cell that has two read ports and one write port

A multi-port SRAM consists of arrays of bit cells. The state of each bit cell is stored in pair of inverters. Data is read out via NMOS transistor to a bit line. Data is written by shorting one side or the other of the inverter pair to ground through a two-NMOS stack, thus storing either 1 or 0. Consequently, read ports require one and write ports require four transistors per bit. Each port has a decoder consisting of AND gates that drive word lines, with one gate per word line.

In a typical simple array, a horizontal word line causes a row of cells to put their data on vertical bit lines, which are converted by sense amplifiers at the bottom into full-swing logic levels. Larger register files may be constructed from mirrored and rotated simple arrays.

The crossed inverters take time to settle after a write, during which a read may not be possible. To mitigate this, multiplexers are commonly used to bypass written data to the read ports upon simultaneous read and write to the same entry.

A RAM is usually pitch-matched to the datapath it serves, but every unit in the data path must have the same bit pitch and therefore every unit has the pitch of the widest unit, which often is the RAM itself.

See also

• Register file