Talk:Replay system
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[edit]Before anyone flies off the handle, please take a look at the source article. Thanks.the1physicist 20:33, 20 November 2005 (UTC)
Other x86 processors
[edit]I need to find good references for this but my understanding is that a similar system does exist on newer processors. In order to make the best usage of bypass buses, dependent uops should be scheduled such that they start to execute when their dependency finishes executing. Not all uops have a known latency though so a uop may try to execute then be replayed if it fails the first time due to data not being ready. The canonical example that I hear cited most often is that a uop that depends on a load will try to execute at the L1 latency after the load and be replayed if the load was a miss. I have have only heard the term replay be used for this so it seems at least related to this article even if it is different than how it worked on the P4. I haven't heard it used outside of x86 processors but that doesn't mean that it doesn't exist. Here's a StackOverflow post that discusses reply on modern systems. In general, that wouldn't be a good source but I trust Peter Cordes and BeeOnRope to be accurate most of the time so I consider this a case of finding good sources. — Bryce (Talk) 22:13, 6 May 2024 (UTC)
Generally, Stackoverflow is not a very good source. However, there are very few sources for this since it is a niche microarchitectural optimization. I wouldn't be surprised if there were patents on this and I haven't scoured the M1 explainer to check if anything is known about this on Apple's CPUs, but information about this in more modern CPUs is sparse. Peter Cordes is very well-known within this area and probably one of the most prominent experts. However, almost all of the very useful and valuable information that he has published is on Stackoverflow. I'd love to look for more sources in the future but for now, I think this is a good start. — Bryce (Talk) 21:13, 14 February 2026 (UTC)