Talk:PCI Express

"full-size" -- 10W vs 25W

https://en.wikipedia.org/wiki/PCI_Express#Power

the 1st bulleted item says x1 cards are limited to 10W.
the 3rd bulleted item says "full-size"  x1 cards may make a grab for 25W.

but what is "full-size"? it is nowhere defined in this article. that is not an official term.

"PCI Express® Card Electromechanical Specification Revision 2.0" section "4.2. Power Consumption" explains the 10W limitation exists for HALF-LENGTH  x1 cards; those which are less than 7 inches deep. the reason is for heat dissipation via simple convection.

snippet:

Notes: 1. A standard height x1 add-in card intended for desktop applications is limited in length to a half-length add-in card and 10 W maximum power dissipation. A standard height x1 add-in card intended for server I/O applications with 25 W maximum power dissipation must be greater than or equal to 177.80 mm (7.0 inches) in length, but must not exceed a full-length add-in card. See Table 6-1 for add-in card size definitions. The same server I/O add-in card must, at initial power-up, not exceed 10 W of power dissipation, until configured as a high power device, at which time it must not exceed 25 W of power dissipation. Refer to Chapter 6 of the PCI Express Base Specification, Revision 1.1 for information on the power configuration mechanism.

"PCI Express® Card Electromechanical Specification Revision 3.0" section "4.2. Power Consumption" maintains the ordinary half-length  x1 card's 10W limit, but increases other cards' limits to 75W after configuration.

snippet:
• A x1 standard height, half-length card is limited to a 10 W maximum power dissipation.
• A x1 low profile card is limited to a 10 W maximum power dissipation.
• A x1 standard height, full-length card is limited to a 10 W maximum power dissipation at initial power up. When the card is configured for high power, by default, it must not exceed a 25 W maximum power dissipation or optionally it must not exceed a 75 W maximum power dissipation. A x4/x8 or a x16 standard height or low profile card is limited to a 25 W maximum power dissipation at initial power up. When a card is configured for high power, it must not exceed a 75 W maximum power dissipation.


As can be seen, the Revision 3.0 info (circa 2013) substantially supersedes the content in this Wikipedia article https://en.wikipedia.org/wiki/PCI_Express#Power which is at this point woefully obsolete and inaccurate.

Cabling

The 'cabling' section stops at OCuLink-2; it looks like PCI-SIG put out standards in early 2024 for PCIe 5.0 (and 6.0) cabling: https://www.anandtech.com/show/21379/pcisig-completes-copprlink-cabling-standard-pcie-50-60-get-wired. This round is called 'CopprLink', not 'OCuLink' -- no more allusion to a dream of eventually including optical cabling. 135.180.194.206 (talk) 06:36, 19 May 2024 (UTC)

Should add: the linked article notes that there is a working group established last year to create an optical cabling standard--so they haven't dropped the dream so much as separated it from the standard they're calling CopprLink.

Basic computer components table

I notice in Basic computer components table in bottom of page that SATA and nvme is put together after SSD which implied they are different version of same thing. They are not.

-SATA is physical bus (the comparison is pcie)

-nvme is the communication protocol FOR bus (the comparison is AHCI)

I don't know wikip structure enough to make change but it seem this only the case for table under PCI Express article. It doesn't appear like this in other article Hyoroemon2 (talk) 03:42, 27 October 2025 (UTC)

The Template:Basic computer components does not imply such a thing. It simply lists SSDs as components and then points out different variants. --Zac67 (talk) 06:17, 30 October 2025 (UTC)

PCIe 1.0 vs. PCIe 1.1

Hi, reading through this articel, I found a minor issue in the section about PCIe 1.1 and its compatability to PCIe 1.0. While for add-in cards this generally is true, it might be an issue with the slots. In the original PCIe Base Specification Revision 1.0, the pin B3 was marked as reserved, meaning implementers had to not connect it. This was changed with the introduction of revision 1.1, were the pin B3 was assigned to the 12V pool.

Hope this will help.

KR ~2026-28436-41 (talk) 09:26, 12 May 2026 (UTC)