Talk:Memory timings

Lower timings to performance

I'm not a memory specialist, but I think your explanations conflict with another article on wikipedia. Based on what you say, lower timing values would mean faster memory access. But, in this article: http://en.wikipedia.org/wiki/DDR2_SDRAM there is a table showing lower timings for lower performance memories and higher timings for higher performance memories. It's hard to believe that fastest memories wait more for data access. Something is wrong or missing in your article.

This is because these numbers are not absolute, but are related to the clock speed -- these are the number of clock cycles of delay. So, for example, the actual delays for 5-5-5 @ 333 MHz works out to almost exactly the same as 4-4-4 @ 266 MHz (about 15 nanoseconds each). Or to think of it another way -- as you speed up the I/O clock, you need to wait more clock cycles in order to wait the same amount of time. —Preceding unsigned comment added by 216.165.144.215 (talk) 09:17, 25 January 2010 (UTC)

Increasing memory bandwidth, multiple processors/execution threads.

I'll argue that due to pipelined nature of modern CPUs and the pre-fetch stages in those pipelines, the latency of RAM is only important if the prefetch stage fails to pre-fetch or if it hangs on a pre-fetch or regular fetch while waiting for RAM. Obviously, such occurrences will slow down a CPU's execution for a number of clock cycles. And I recommend some adventurous wikipedian will find a proper source to confirm this and include it in the article. 22:00, 28 January 2016 (UTC) — Preceding unsigned comment added by 2001:981:9B5E:1:3DA5:DFB3:7175:7EFB (talk)

Correction to "Memory timings"

The article says "In SDRAM modules, it [tRAS] is simply TRCD + CL." This is incorrect.

- tRAS specifies the time that needs to pass for a Precharge to be issued to a bank after an Activate. Fundamentally, this has nothing to do with tCL, which specifies the amount of time to transfer data from the I/O circuitry of DRAM to the bus.

- tRCD specifies the minimum amount of time that needs to pass to issue a Read/Write after an Activate. It is smaller than tRAS.

For a clear description of the major DRAM timing parameters and how they relate to each other, I would suggest looking at Section 2 (Figures 5-6 and Table 2) in the following paper:

Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, and Onur Mutlu, "Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture" Proceedings of the 19th International Symposium on High-Performance Computer Architecture (HPCA), Shenzhen, China, February 2013. https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf — Preceding unsigned comment added by 188.155.143.48 (talk) 10:40, 29 October 2016 (UTC)