Talk:Emerald Rapids
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Feedback from New Page Review process
[edit]I left the following feedback for the creator/future reviewers while reviewing this article: Thanks for the article!.
Intel's Four Takeaways from Intel’s Investor Webinar
[edit]Here is an article about the fifth generation Xeon Scalable processors at Four Takeaways from Intel’s Investor Webinar. Rjluna2 (talk) 16:55, 1 April 2023 (UTC)
Intel Unveils Future-Generation Xeon with Robust Performance and Efficiency Architectures
[edit]Here is an article on Intel Unveils Future-Generation Xeon with Robust Performance and Efficiency Architectures. Rjluna2 (talk) 15:46, 29 August 2023 (UTC)
Intel Innovation 2023: Empowering Developers to Bring AI Everywhere
[edit]Here is an article that discuss about E-core processor with 288 cores from Intel Innovation 2023: Empowering Developers to Bring AI Everywhere. Rjluna2 (talk) 20:11, 22 September 2023 (UTC)
Discipline and Process Built Emerald Rapids
[edit]A senior principal engineer, data center processor architecture, Irma Esmer Papazian explains the process of the 5th Generation Xeon processor as described at Discipline and Process Built Emerald Rapids. Rjluna2 (talk) 18:59, 27 December 2023 (UTC)
- May I ask about your apparent obsession with her? Personally I don't believe she is important enough to warrant mentioning in the article. Is she your relative?
- @Rjluna2 Digital27 (talk) 02:38, 28 December 2023 (UTC)
- No, this is in reference to her work on this generation Xeon microprocessor. Rjluna2 (talk) 13:50, 28 December 2023 (UTC)
- Thanks for your reply! Are you suggesting that we add the reference to the Intel document or to her into the WP article? Digital27 (talk) 08:55, 29 December 2023 (UTC)
- It goes both ways. She is one of these people who are involved with implementing the performance and efficiency on this generation silicon design. Like anyone else who worked with these microprocessors/microcontrollers that we write at this site from their companies that is from the past into the future. Rjluna2 (talk) 13:30, 30 December 2023 (UTC)
- Thanks for your reply! Are you suggesting that we add the reference to the Intel document or to her into the WP article? Digital27 (talk) 08:55, 29 December 2023 (UTC)
- No, this is in reference to her work on this generation Xeon microprocessor. Rjluna2 (talk) 13:50, 28 December 2023 (UTC)
Instruction level support
[edit]According to GCC 13 source (https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/common/config/i386/i386-common.cc;h=988805a3aeddce9952a3256b279e081877909c7a;hb=refs/heads/releases/gcc-13#l2083) Emerald Rapids is using the same instruction level support as Sapphire Rapids including AMX which is missing from current article's General information section. There is also inconsistencies between Sapphire and Emerald articles in terms of Instruction and Extension: Emerald has AES-NI as Extension while Sapphire as Instruction. The latter is correct. 188.47.113.184 (talk) 16:41, 29 December 2023 (UTC)