gem5
| gem5 | |
|---|---|
 | |
| Developer | Community contributors |
| Release | August 2011 |
| Stable release | v25.1.0.1
/ April 21, 2026 |
| Written in | C++, Python |
| Operating system | Linux, macOS |
| Platform | x86-64, ARM64 |
| License | BSD 3-Clause |
| Website | www |
| Repository | github |
The gem5 simulator is an open-source discrete-event computer architecture simulator used for computer-system and microarchitectural research.[1][2] It is widely used in academic and industrial computer-architecture research.[2] gem5 models components of computer systems, including processors and memory hierarchies, allowing researchers to evaluate hardware configurations and architectural designs in software.[1][2]
gem5 supports both full-system simulation, in which a complete operating system runs on the simulated hardware, and syscall-emulation mode, in which user-space programs run without a simulated operating-system kernel.[1] It supports several instruction set architectures (ISAs), including x86, Arm, RISC-V, MIPS, SPARC, and Power, as well as a range of processor and memory-system models.[1][2] Simulated systems are configured primarily through Python, while most of the simulator itself is implemented in C++.[1]
History
[edit]gem5 was created through the merger of the m5 processor and system simulator and the GEMS memory-system simulator. The combined simulator was released in 2011.[3] m5 contributed the simulation framework, processor models, instruction-set support, and device models, while GEMS contributed the Ruby memory-system model, including cache-coherence and interconnection-network modeling.[3]
Design and capabilities
[edit]gem5 is an event-driven simulator in which simulated components schedule events representing changes in the modeled system.[2] It provides processor models at different levels of detail, including simple functional and timing models, an in-order pipelined model, and an out-of-order processor model.[2]
The simulator provides two principal approaches to modeling memory systems. Its classic memory system allows caches and interconnects to be assembled into configurable memory hierarchies, while the Ruby memory system provides more detailed modeling of cache-coherence protocols and interconnection networks.[3][1]
gem5 can operate in full-system mode, where it models sufficient hardware to boot an operating system, or in syscall-emulation mode, where operating-system services required by an application are provided by the simulator.[1] Its modular design allows processor, memory, interconnect, and other system components to be configured or replaced for architectural experiments.[1]
See also
[edit]References
[edit]- 1 2 3 4 5 6 7 8 Lowe-Power J, Ahmad AM, Akram A, Alian M, Amslinger R, Andreozzi M, Armejach A, Asmussen N, Beckmann B, Bharadwaj S, Black G, Bloom G, Bruce BR, et al. (2020). "The gem5 Simulator: Version 20.0+". arXiv:2007.03152 [cs.AR].
- 1 2 3 4 5 6 Akram, Ayaz; Sawalha, Lina (2019). "A Survey of Computer Architecture Simulation Techniques and Tools". IEEE Access. 7: 78120–78145. doi:10.1109/ACCESS.2019.2917698.
- 1 2 3 Binkert, Nathan; Beckmann, Bradford; Black, Gabriel; Reinhardt, Steven K.; Saidi, Ali; Basu, Arkaprava; Hestness, Joel; Hower, Derek; Krishna, Tushar; Sardashti, Somayeh; Sen, Rathijit; Sewell, Korey; Shoaib, Muhammad; Vaish, Nilay; Hill, Mark D.; Wood, David A. (2011-08-31). "The gem5 simulator". ACM SIGARCH Computer Architecture News. 39 (2): 1–7. doi:10.1145/2024716.2024718.
External links
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