Draft:Wladek Grabinski

• Comment: Based upon his publication record there is no indication of a pass of WP:NPROF. The page does not indicate enough WP:SIGCOV for a pass of WP:GNG, and I see no indications from a search. Note that writing an autobiography and not declaring it is against Wikipedia policy. Ldm1954 (talk) 13:53, 10 February 2026 (UTC)

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Władysław Grabiński
Born	(1960-05-20)May 20, 1960 Chełm, Poland
Alma mater	Institute of Electron Technology, Warsaw
Scientific career
Fields	Compact/SPICE device modeling Verilog-A Standardization RF and analog IC simulation
Institutions	ITE Warszawa ETHZ EPFL Motorola Freescale Semiconductor IHP Microelectronics
Thesis	(1991)

Władysław "Władek" Grabiński is a Polish electrical engineer and semiconductor specialist known for work in compact transistor modeling, integrated circuit (IC) simulation, and device characterization for analog and RF applications. His research focuses on MOSFET and bipolar transistor compact models, parameter extraction, and high-frequency device characterization. He is active as an independent consultant collaborating with European research institutions and semiconductor foundries, including IHP Microelectronics.

Early life and education

Grabiński was born in Chełm, Poland. He completed his doctoral studies in electronics at the Institute of Electron Technology (ITE) in Warsaw, receiving his Ph.D. degree in 1991 [1]. His doctoral research focused on electrical characterization of semiconductor devices and process technologies.

Research and career

From 1991 to 1998, Grabiński worked as a Research Assistant at the Integrated Systems Laboratory (IIS) at ETH Zurich, Switzerland, where he supported CMOS and BiCMOS technology development through electrical characterization of semiconductor processes and devices.

Between 1999 and 2000, he was affiliated with the Laboratory of Electronics and Microsystems (LEG) at EPFL (École Polytechnique Fédérale de Lausanne), continuing research in semiconductor TCAD and compact modeling.

He later joined Motorola and subsequently Freescale Semiconductor in Geneva, working in their device modeling centers. His work focused on compact transistor modeling, parameter extraction, and SPICE model development for industrial semiconductor processes.

Grabiński has also worked as an independent consultant and has collaborated with IHP (Innovations for High Performance Microelectronics), contributing to the OpenPDK initiative [2]. He has been involved in Verilog-A model standardization and is associated with the MOS-AK Association , an international professional group focused on the compact/SPICE modeling of the MOSFET device modeling.

Awards and honours

• IEEE EDS Senior Member
• IEEE EDS R8 Chair

Select publications

[1] Grabiński, Władysław (1991). Metody wyznaczania gęstości pułapek powierzchniowych w strukturach MOS z uwzględnieniem niejednorodnego profilu domieszkowania (Praca doktorska) (in Polish). Polska: Instytut Technologii Elektronowej.

[2] Grabinski, W. (2025). "The IHP OpenPDK Initiative: The Status and Roadmap". 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM). Hong Kong: IEEE. pp. 1–3. doi:10.1109/EDTM61175.2025.11041228.

[3] Grabinski, Wladek; Tomaszewski, Daniel (2024). "Compact/SPICE Modeling". In Rudan, Massimo; Brunetti, Riccardo; Reggiani, Silvano (eds.). Springer Handbook of Semiconductor Devices. Springer. doi:10.1007/978-3-030-79827-7_34.

Bibliography

• "Dr Władysław Grabiński". archiwalna baza „Ludzie nauki” portalu Nauka Polska (OPI PIB). Retrieved 2026-02-08.

References

Category:Living people Category:Year of birth missing (living people) Category:Polish electrical engineers Category:Semiconductor device researchers Category:ETH Zurich alumni Category:EPFL alumni