Draft:KX-8-CPU

• Comment: In accordance with Wikipedia's Conflict of interest guideline, I disclose that I have a conflict of interest regarding the subject of this article. The best-KX (talk) 21:04, 18 July 2026 (UTC)

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KX‑8 CPU

The KX‑8 CPU is a fictional 8‑bit microarchitecture known for its highly granular instruction set, advanced peripheral control, and bold claims of extreme performance. Within its design community, it is often described as one of the most powerful CPUs ever built, capable of running complex programs, advanced simulations, and even rendering 3D graphics despite its minimalist 8‑bit foundation.

Overview

The KX‑8 CPU is built around a unified system bus, a multi‑mode ALU, a four‑register general‑purpose bank, and tightly integrated GPU and display subsystems. Its instruction set is fully binary‑encoded, with each opcode directly controlling hardware‑level signals such as SR latches, register enables, and bus gates.

Architecture

Registers

• A, B — Primary ALU input registers
• X, Y — General‑purpose registers used for addressing, GPU coordinates, and intermediate values
• MAR — Memory Address Register
• MDR — Memory Data Register
• PC — Program Counter

Bus System

All data movement occurs through a shared bus. Registers can be enabled onto the bus or loaded from it using dedicated opcodes.

Instruction Set

Below is the complete instruction set used by the KX‑8 CPU.

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ALU Instructions

• 00000000 — NOP — No operation
• 00000001 — ADD — Set ALU to addition mode
• 00000002 — SUB — Set ALU to subtraction mode
• 00000003 — AND — Set ALU to AND mode
• 00000004 — OR — Set ALU to OR mode
• 00000005 — XOR — Set ALU to XOR mode
• 00000006 — NOT — Set ALU to NOT mode
• 00000007 — RESERVED

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Register → Bus (Enable)

• 00000008 — Enable Y
• 00000009 — Enable X
• 00000010 — Enable B
• 00000011 — Enable A

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Bus → Register (Load)

• 00000012 — Load A — Latches A from bus via SR
• 00000013 — Load B — Latches B from bus via SR
• 00000014 — Load X — Latches X from bus via SR
• 00000015 — Load Y — Latches Y from bus via SR

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Disable Register Load (Unload)

• 00000016 — Unload Y — Unlatches Y via SR reset
• 00000017 — Unload X — Unlatches X via SR reset
• 00000018 — Unload B — Unlatches B via SR reset
• 00000019 — Unload A — Unlatches A via SR reset

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ALU Input Select

• 00000020 — Enable ALU Input A
• 00000021 — Enable ALU Input B

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RAM / Memory Instructions

• 00000022 — Load MAR — Load address register
• 00000023 — Enable MAR — Put MAR on bus
• 00000024 — Load MDR — Load data register
• 00000025 — Enable MDR — Put MDR on bus
• 00000026 — RAM READ — Read from RAM
• 00000027 — RAM WRITE — Write to RAM

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Program Counter / Flow Control

• 00000028 — Enable PC
• 00000029 — Load PC
• 00000030 — Increment PC
• 00000031 — JMP — Jump to operand
• 00000032 — JZ — Jump if zero
• 00000033 — JNZ — Jump if not zero

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Input

• 00000034 — IN — Activates SR latch to read keyboard input onto bus

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Output

• 00000035 — OUT — Resets input SR latch, allowing operand to pass through ROM again

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8×8 Screen Drawing (GPU)

• 00000036 — SETX — Set GPU X register
• 00000037 — SETY — Set GPU Y register
• 00000038 — SETPIX — Set pixel state (1 = on, 0 = off)
• 00000039 — DRAW — Draw pixel at (X,Y) using SETPIX
• 00000040 — CLEAR — Clear entire screen

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7‑Segment Display

• 00000041 — SEGSET — Set display data
• 00000042 — SEGIDX — Select which of 10 displays to update

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Operand Control

• 00000043 — Operand Enable Lock — Locks operand from entering bus
• 00000044 — Operand Disable Lock — Locks operand from leaving bus

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Performance Claims

Although fictional, the KX‑8 CPU is described as:

• Capable of running powerful programs such as calculators, games, and multi‑stage simulations
• Able to drive 3D graphics, despite its 8‑bit nature
• One of the most powerful CPUs ever built within its design universe

Its architecture emphasizes direct hardware control, making it ideal for educational CPU design, retro‑style computing, and experimental low‑level programming.

prototype of KX

The KX‑8 Prototype CPU is an experimental 8‑bit microprocessor system constructed entirely on interconnected breadboards. It represents the first physical implementation of the KX‑8 architecture, a design noted for its extensive opcode set, integrated GPU subsystem, and direct hardware control through SR‑latch logic. The prototype is regarded as one of the most powerful 8‑bit CPUs ever built, capable of running complex programs and rendering 3D graphics.

Conclusion

The KX‑8 CPU currently exists in two forms: a fully wired breadboard prototype and a complete digital simulation built in Logisim. The breadboard version serves as the first physical implementation of the architecture, demonstrating the CPU’s instruction set, display systems, memory interface, and GPU capabilities in real hardware. Despite being a prototype, it is capable of running complex programs, driving multiple 7‑segment displays, and rendering pixel‑based graphics such as 3D cubes.

The final production version of the KX‑8 CPU is planned for construction in the near future. This upcoming revision will transition the design from breadboards to a dedicated printed circuit board (PCB), integrating all subsystems—including the ALU, register bank, RAM controller, GPU module, and display drivers—into a compact and stable hardware platform. The PCB version is expected to offer higher clock speeds, improved reliability, and expanded graphical capabilities.

Until the physical final version is completed, the Logisim simulation remains the primary development environment. It is used to test new opcodes, verify timing behavior, refine bus control, and validate GPU drawing logic. The simulation ensures that the architecture is fully stable before fabrication begins, making it an essential step in the KX‑8’s development cycle.