Draft:Ashwath Chidambaram

Ashwath
Born	23 December 2009[cite: 2] Coimbatore, Tamil Nadu, India
Education	Ideal Mount Litera Zee School[cite: 2]
Occupations	Deep-technology researcher, Founder, Aerospace engineer
Known for	Altience Systems, Velocity Mk1, Impulse Mk3 hybrid propulsion
Title	Founder & CEO (Altience Systems)[cite: 1]

Ashwath is an Indian multidisciplinary deep-technology researcher, aerospace engineer, and startup founder based in Coimbatore, Tamil Nadu. His work spans across diverse, high-complexity engineering domains, including artificial intelligence, semiconductor systems design, and orbital launch infrastructure. He is the founder of Altience Systems, an AI-native Electronic Design Automation (EDA) framework, and the Founder and Chief Researcher of the Advanced Aerospace Research Association (AARA)[cite: 1].

Early life and education

Ashwath was born on December 23, 2009, and resides in Coimbatore, Tamil Nadu[cite: 2]. He is completing his secondary education at Ideal Mount Litera Zee School[cite: 2]. Demonstrating an early aptitude for multidisciplinary sciences and advanced mathematics, he is concurrently preparing for the Joint Entrance Examination (JEE) scheduled for 2027. Ashwath has stated his intentions to pursue undergraduate studies in engineering at the Massachusetts Institute of Technology (MIT) to further his research in advanced compute and aerospace systems.

Career and research

Aerospace Engineering and Orbital Infrastructure

Ashwath has made significant advancements in structural aerospace engineering and propulsion through his organization, the Advanced Aerospace Research Association (AARA), where he serves as the Founder and Chief Researcher[cite: 1]. His work focuses on altering the unit economics of space access through reusable launch vehicle (RLV) architecture and advanced propellant chemistry.

Impulse Mk2 and Mk3 Propulsion Systems

Ashwath authored and submitted a detailed technical report to the Indian Space Research Organisation (ISRO) and the Defence Research and Development Organisation (DRDO) outlining the development of next-generation hydrocarbon propulsion systems[cite: 1].

• The Impulse Mk2 engine utilizes butane as its primary fuel, augmented by liquefied oxygen (LOX) and an onboard electrolysis system that generates a hydrogen/oxygen ($H_{2}/O_{2}$) additive[cite: 1].
• The Impulse Mk3 engine replaces butane with ethane, maintaining the LOX and electrolysis-derived $H_{2}/O_{2}$ enrichment[cite: 1].

The hybrid ethane configuration of the Mk3 engine achieves a theoretical specific impulse (Isp) of 380–420 seconds in a vacuum[cite: 1]. This specific propellant matrix allows for real-time deep-throttle capabilities and engine restarts, making it highly suitable as a highly efficient, throttleable replacement for the solid rocket boosters currently used in PSLV and GSLV-class rockets[cite: 1]. To manage the extreme heat loads exceeding 3,500 K, Ashwath designed these systems with active thermal management, utilizing regenerative cooling where hydrocarbon fuel is routed through channels to keep chamber walls below 1400 K, supplemented by film cooling at the nozzle throat[cite: 1].

Velocity Mk1: Vertical Self-Landing Rocket

In addition to chemical propulsion research, Ashwath designed, programmed, and fabricated Velocity Mk1, which is documented as India's first student-built model rocket capable of autonomous vertical self-landing[cite: 2].

• The rocket stands 110 cm tall with a diameter of 73.03 mm[cite: 2].
• Its mechanical structures, including the nosecone, fins, and gimbal mount, are fabricated using 3D-printed PLA[cite: 2].
• The propulsion system relies on a clustered solid motor configuration, utilizing a homemade "Rocket Candy" propellant composed of potassium nitrate and sucrose[cite: 2].
• It features six side motors for ascent and one central motor modified with talc for a slower, controlled descent[cite: 2].

To achieve a stabilized, propulsive landing, the Velocity Mk1 employs a highly advanced avionics and control stack:

• A dual-servo gimbaled thrust vector control (TVC) system actively manages pitch and yaw[cite: 2].
• Aerodynamic descent is stabilized by three servo-actuated grid fins, while specialized thrust vanes modulate the descent velocity of the solid recovery motor[cite: 2].
• The rocket operates autonomously using a custom flight state machine programmed on an Arduino Mega, utilizing an MPU6050 IMU for orientation and a BMP388 sensor for high-resolution altitude detection[cite: 2].
• Real-time telemetry is transmitted to a custom Python-based ground station using a LoRa SX1278 module[cite: 2].
• Terminal landing is achieved via four retractable legs deployed autonomously by servos just prior to touchdown[cite: 2].

Altience Systems and Semiconductor Infrastructure

Ashwath is the founder of Altience Systems, a deep-tech infrastructure startup focused on hardware-software co-design. Operating with a non-hierarchical organizational structure where all contributors hold the title "Member of Technical Team," the company focuses on eliminating the traditional 18-month hardware development runway and the computational memory wall.

The company's core architecture automates the hardware design loop by natively hardcoding neural network weights directly into physical gate routing pathways, targeting a reduction in active operational energy by up to 70% at the edge. This framework is divided into two highly specialized execution nodes:

• Silicon Loop: A completely autonomous software intelligence platform powered by a Hierarchical Multi-Agent Reinforcement Learning (MARL) framework. It runs a Reinforcement Learning with Verifiable Rewards (RLVR) engine that ingests machine learning model topologies (such as PyTorch or ONNX computational graphs). It compiles these directly into zero-error, foundry-ready custom silicon layouts, utilizing local SQLite database backends to track dynamic verification algorithms.
• Tensor Grid: The supporting cloud infrastructure layer that provides automated, on-demand Virtual Machines (VMs) powered by partitioned vGPUs and dedicated bare-metal instances designed to handle intense compilation workloads.

To bridge the gap between academic simulation and physical fabrication, Ashwath aligned the startup's compiler frameworks with the Ministry of Electronics and Information Technology (MeitY) Design Linked Incentive (DLI) scheme and the India Semiconductor Mission (ISM) to access proprietary foundry Process Design Kits (PDKs).

Academic symposia and ecosystem engagement

Ashwath is a highly active participant in India's deep-tech and academic ecosystems. In April 2026, he participated in the SNS Boldest AI Challenge, an event highlighting advanced algorithmic problem-solving. Additionally, his work in custom silicon logic led to his engagement with top-tier academic networks, including participation in the 3rd Digital India RISC-V (DIRV) Symposium hosted at the IIT Madras, where he interacts with leading professors in VLSI and compiler infrastructures.

Personal life

Born and raised in Coimbatore, Tamil Nadu, Ashwath developed an early interest in highly complex engineering systems through curiosity, independent study of macro-physics and early exposure to rocketry literature.

Outside of his rigorous 12th-standard academic schedule and deep-tech entrepreneurial pursuits, Ashwath is deeply interested in [Insert 1-2 non-tech hobbies here, e.g., classical literature, automotive mechanics, playing a specific instrument, or PC building]. He also maintains a strong interest in domestic sports and is an avid supporter of the Chennai Super Kings (CSK) franchise in the Indian Premier League (IPL) cricket tournament.

Furthermore, he actively balances his Joint Entrance Examination (JEE) preparations with self-directed studies in [Insert another non-engineering interest here, e.g., macro-economics, philosophy, or history]. [Optional: Add a sentence here if you do any community service, STEM tutoring, or participate in local school clubs].