RH-32
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The RH-32 was a radiation-hardened 32-bit MIPS R3000 based microprocessor chipset developed by the USAF Rome Laboratories[1] for the Ballistic Missile Defense Agency, and produced by Honeywell (later, TRW) for Aerospace applications. It achieves a throughput of 20 MIPS. It was a three-chip set, consisting of Central Processing Unit, Floating Point Unit, and Cache Memory.[2]
References
[edit]- ↑ Schechter, Joanne (September 5, 1991). "Will commercial strategy deliver cost, time savings?". EDN. Archived from the original on September 24, 2015 – via HighBeam Research.
- ↑ G.R. Brown, L.F. Hoffmann, S.C. Leavy, J.A. Mogensen, J. Brichacek (1997-07-24). "Honeywell radiation hardened 32-bit processor central processing unit, floating point processor, and cache memory dose rate and single event effects test results". 1997 IEEE Radiation Effects Data Workshop NSREC Snowmass 1997. Workshop Record Held in conjunction with IEEE Nuclear and Space Radiation Effects Conference. IEEE. pp. 110–115. doi:10.1109/REDW.1997.629808. ISBN 0-7803-4061-2. S2CID 60521143.
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