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// Workers AI · dad joke modeWhat did SC/MP say to the bit? "You can't byte off more than we can chip.

From Wikipedia, the free encyclopedia
(Redirected from SC/MP)
National Semiconductor SC/MP
PMOS SC/MP (ISP-8A/500)
General information
LaunchedApril 1976; 50 years ago (April 1976)
Common manufacturer
Performance
Max. CPU clock rate1 MHz to 4 MHz
Data width8 bits
Address width16 bits
Physical specifications
Package
Architecture and classification
Number of instructions46
History
SuccessorsSC/MP-II (INS8060)
70-Series (INS807x)

National Semiconductor's SC/MP (pronounced scamp) for Simple Cost-effective Micro Processor, is an early 8-bit microprocessor which became available in April 1976. It was designed to allow systems to be implemented with the minimum number of additional support chips. SC/MP included bus-access control signals that allowed several processors to share a common memory bus in a daisy-chained multiprocessor arrangement, or to support direct memory access hardware.

The SC/MP was followed by the SC/MP-II, also known as the INS8060. National Semiconductor later introduced the 70-Series (also known as the INS8070 Series).[1][2] Some later sources refer to this family as “SC/MP III” or “SC/MP-3”,[3] terminology not used in contemporary National Semiconductor documentation.[1][2]

The programmer-visible model comprises an 8-bit accumulator, an 8-bit extension register, an 8-bit status register, and four 16-bit pointer registers, one of which is used as the program counter. Memory-reference addressing is page-based, with address arithmetic performed on the low 12 bits of the address.[4][5]

Designed to be as low-cost as possible, the SC/MP emphasized simple control logic and built-in multiprocessor bus arbitration. It is significantly slower than contemporary designs like the Intel 8080 or MOS 6502.[a] Another oddity was that the program counter could only increment the lower 12-bits of the 16-bit address; the upper 4-bits had to be set using special instructions. The result was that instructions accessed main memory as sixteen 4 KB "pages" and reaching memory outside those pages required multiple instructions.

The combination of slow speed and paged memory limited its attractiveness outside the embedded markets it was aimed at, and in this market it competed against the Fairchild F8 which had a number of useful additional features and cost less than a dollar more at 100-unit quantities. The system saw relatively little use. Signetics was identified as an authorized second source and published SC/MP-II documentation, but it is unclear whether it manufactured any SC/MP devices.

Design

[edit]

The SC/MP instruction set consists of 46 instructions.[4]

NS SC/MP registers
Main registers
  7 6 5 4 3 2 1 0 (bit position)
  AC Accumulator
  E Extension
Pointer registers
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position)
page field
bits 15–12		 12-bit address within page
bits 11–0
P0/PC Program Counter
P1 Pointer 1
P2 Pointer 2
P3 Pointer 3
Status Registers
  7 6 5 4 3 2 1 0 (bit position)
  CY/L OV SB SA IE F2 F1 F0 Status Register (SR)


ALU and main registers

[edit]

The arithmetic logic unit (ALU) is accumulator-based, with a single 8-bit accumulator, AC. National Semiconductor described the SC/MP's arithmetic as parallel, binary, fixed-point and two's-complement, with support for two-digit BCD addition using the DAE (Decimal Add Extension) instruction.[4][6]

A second 8-bit register, "Extension", or E, is an 8-bit auxiliary to the accumulator (AC), but unlike AC, it is not a general-purpose register. It cannot be loaded directly from memory and is accessed only through a small set of single-byte instructions that operate between E and AC.

Two of these, LDE and XAE, move or exchange data between the two registers. The others, ANE, ORE, XRE, ADE, DAE, and CAE use the contents of E as the second operand in arithmetic or logical operations on AC.[7][8]

The E register also serves several other roles in the architecture. It functions as the shift register for the serial I/O system, used by the SIO instruction. Each execution shifts E right by one bit, placing the least-significant bit on the SOUT pin and shifting in a new bit from SIN. Transmitting or receiving a full byte requires repeated SIO instructions. To transfer serial data to or from memory, values can be exchanged between E and AC. Logical operations on AC can then test or mask values read into E.[9][10][11]

The E register can also be used in place of the displacement byte in PC-relative, indexed, and auto-indexed memory-reference instructions. In these forms, the usable literal displacement range is effectively −127 to +127. The byte value 80 hexadecimal is reserved as a special marker, so it does not mean a literal displacement of −128. Instead, it tells the processor to use the contents of E as the displacement when forming the effective address.[12][13]

The separate Status Register (SR) is 8 bits wide. Its three least-significant bits, 0 through 2, are available on control-output pins, providing an easy way to output single-bit signals. Bits 4 and 5 reflect the external Sense A and Sense B input pins. These bits can be read by copying SR to AC with CSA, but they are read-only inputs and are not changed by CAS. When interrupts are enabled, Sense A also serves as the interrupt request input. Bit 3 is the Interrupt Enable bit, which can be cleared with DINT, set with IEN, or changed by copying AC to the writable status bits with CAS. Bits 6 and 7 are the overflow flag and carry/link flag. Although there is no explicit zero flag, zero is determined from the current content of AC.[14][15][16]

Addressing and pointer registers

[edit]
PMOS SC/MP die (ISP-8A/500)

Like most 8-bit microprocessors of the era, the SC/MP is based around a 16-bit address bus and an 8-bit data bus. To reduce pin count, the external address bus contains only 12 pins, multiplexing 4 pins on the data bus to create a complete 16-bit address.[17] The processor only directly modifies the lower 12-bits of the program counter. There are separate instructions to set the upper four bits by copying an 8-bit value into the high byte. This provides a memory map of sixteen four-kilobyte pages. PC-relative or indexed addressing cannot refer to code or data outside the current 4 KB page.[12] This leads to a curiosity of the design: when the program counter reaches the end of a page, it does not move to the next page, it returns to the start of the current page.[17]

Addressing is further limited by the two-byte instruction format used by most memory-reference instructions, which places the opcode in one byte and a displacement in the second. National Semiconductor described the displacement field as an 8-bit two's-complement value with an encoded range of −128 to +127 from the selected pointer-register value. In memory-reference instruction forms, however, the byte value 80 hexadecimal is a special marker rather than an available literal displacement of −128. It causes the processor to use the contents of the E register as the displacement source when forming the effective address.[18][12] For instance, an address might refer to a location in memory by saying it is +10 locations from the value in the program counter, or -10 from the value in one of the 16-bit pointer registers. To access a location outside the PC-relative or indexed displacement range, or outside the current 4 KB page, a suitable address has to be explicitly loaded into one of the pointer registers.[12] Because the registers are 16-bit, and the accumulator that loads values is 8-bit, setting a complete address requires several instructions.[19]

As indexed addressing is critical to the addressing model, the SC/MP included four 16-bit pointer registers, P0 through P3. P0 is the program counter. By convention, P1 is normally used as a pointer into ROM, P2 into RAM, and P3 was used to store an address during interrupts and subroutine calls.[20] The SC/MP does not have a hardware stack or dedicated stack pointer for storing return addresses. Subroutine linkage instead uses pointer registers, especially P3 with the XPPC instruction, so nested calls or interrupt handling requires return addresses to be saved explicitly, or by a software stack convention.[21][22][19]

There are four primary addressing modes, PC-relative, indexed, immediate (meaning a constant in the instruction's second byte as opposed to an offset), and auto-indexed. PC-relative addressing is actually the same as indexed, selecting P0 as the pointer register.[12][4]

Auto-indexing aids in the construction of loops. In the auto-indexed form, prefixed with @, the selected pointer register is also modified by the displacement. If the displacement is negative, the pointer register is modified before the memory access. If the displacement is zero or positive, the current pointer-register value is used as the effective address, and the pointer register is modified after the memory access. This removes the need for a separate instruction to change the value in the register, so one could store the starting value of a block of data in memory in a pointer register and then loop through all of the data.[12][23] If the offset is negative, as in @-1(P2), it performs the decrement before accessing the final value. If it is positive, as in @1(P2), it does a post-increment.[19] This predecrement-postincrement behavior makes it possible to create a LIFO stack. Top of stack is accessed with (P2). Stack space can be allocated and released with larger offsets such as @-8(P2) and @8(P2), respectively.

The memory increment/decrement instructions ILD and DLD, and the transfer instructions JMP, JP, JZ, and JNZ, are documented separately from the memory-reference instructions. National's source forms for these instructions include disp and disp(ptr). The auto-indexed form @disp(ptr) is not supported.[24]

Interrupt handling

[edit]

The system includes automatic handling of interrupts on the Sense A line. If Sense A is active when the Interrupt Enable flag, IE, is set, the SC/MP completes the current instruction, clears IE to disable further interrupts, and exchanges the contents of PC and P3. Execution then resumes using the normal SC/MP increment-before-fetch behaviour, so P3 must have been prepared with the address immediately preceding the interrupt handler entry point, subject to the processor's 4 KB page-addressing rules.[25][26]

Because interrupt entry is implemented as an automatic XPPC P3 operation, P3 conventionally serves as the interrupt-link register and is unavailable for general use while interrupts are enabled.[25]

The system does not include the equivalent of a return-from-interrupt. This can be performed with a XPPC P3 instruction, which exchanges the contents of P3 and the program counter. This restores the interrupted program's execution address while storing the current interrupt-handler address in P3, allowing execution to continue where it left off. However, this leaves the wrong address in P3, not the start of the interrupt handler, but the end. To address this, the common solution is to place the XPPC P3 that returns to the main code one instruction above the handler entry point, rather than at the end. When the handler completes, it jumps back to this instruction, so when XPPC P3 is executed, the PC is pointed one location before the proper entry point. Because the SC/MP increments the program counter before instruction fetch, the next interrupt then enters the handler at the correct entry point. This "exit handler" normally also sets the IE to 1 with IEN to re-enable interrupts.[27][28]

Interrupt entry itself is simple, but saving processor state is left to software. National Semiconductor's example interrupt save sequence for the SC/MP requires 17 instructions and 26 bytes of object code, compared with four instructions and four bytes for the Intel 8080.[29]

Bus control

[edit]
National Semiconductor SC/MP Development System

A feature of the SC/MP family was its bus-access logic, using bus-request, enable-input and enable-output signals. In the original PMOS SC/MP documentation these are named BREQ, ENIN and ENOUT; in SC/MP-II / INS8060 documentation the corresponding active-low signals are named NBREQ, NENIN and NENOUT.[30][31] These signals supported external direct memory access (DMA) hardware and allowed multiple SC/MP processors to be connected in a daisy-chained shared-bus arrangement.[30][31] National Semiconductor's PMOS SC/MP documentation gives example DMA and multiprocessor configurations, contrasting an external DMA controller with the SC/MP's built-in bus-access logic.[30] The INS8060 datasheet documents the corresponding SC/MP-II bus-access signals, NBREQ, NENIN and NENOUT, for DMA and multiprocessor use.[31] Williamson and Dale give the equivalent SC/MP-II explanation in the context of the MK14.[32]

In DMA applications, data transfers between memory and a peripheral could be made without the processor being involved in the actual data transfer, apart from control functions.[33] In functional terms, a processor requested the shared bus on its bus-request line and was granted access through its enable-input line. In the PMOS SC/MP documentation, this is described as BREQ high and ENIN high; in the SC/MP-II / INS8060 documentation, the corresponding active-low signals are NBREQ and NENIN.[34][31] For multiprocessor use, the processor's enable-output line was connected to the enable-input line of the next processor in the chain. While one processor controlled the bus, later processors in the chain were locked out; when it released the bus, the enable signal was passed to the next processor. If several processors requested the bus at the same time, they were served in daisy-chain priority order. National noted for the PMOS SC/MP that typically no more than three processors were used in a cascade arrangement without an external priority-logic controller.[35]

Osborne's review of the system stated: "Bus request acknowledge logic coupled with bus access priority logic makes SC/MP the slave microprocessor of choice in any multi-microprocessor application."[36] The market for such configurations appears to have been limited.[citation needed]

Osborne and Kane noted a further consequence of this bus-access design: an SC/MP external bus cycle could be suspended after it had already begun. In their terminology, this included instruction fetch, data input, and data output cycles. If ENIN was withdrawn while the CPU had access to the bus, the SC/MP address and data lines entered the high-impedance state, relinquishing the bus, while BREQ remained asserted. When ENIN was restored, the interrupted cycle would be performed. They also noted that the available SC/MP literature did not specify the exact "point-of-no-return" within the cycle: if the cycle was already nearly complete, the processor might complete it rather than suspend and restart it. This mattered because the read and write strobes, NRDS and NWDS, could in principle be repeated, causing the same data to be read or written twice.[37] The INS8060 datasheet notes special behaviour for ILD and DLD: during these read-modify-write instructions the SC/MP does not relinquish the bus between the read and write phases. If NENIN is deasserted after the load has completed, that load portion is not repeated when NENIN is reasserted.[38]

Unusual features

[edit]

A defining feature of the SC/MP is its page-oriented pointer arithmetic. The program counter, P0, and the three general pointer registers, P1 to P3, are 16-bit registers, but normal address arithmetic operates only on the lower 12 bits. The upper four bits form a page field selecting one of sixteen 4 KB pages. Normal program-counter increments, PC-relative addressing, indexed addressing, and auto-indexing do not carry into this page field. If the lower 12 bits overflow, the address wraps within the same page. The page field changes only when an instruction loads a new value into the high-order part of the register, for example with XPAH, XPPC, or a JMP using an index register pointing to another page.[5][39][17]

The SC/MP does not include a dedicated jump-to-subroutine instruction. National Semiconductor's assembler provides a JS pseudo-instruction that expands into a sequence of five instructions occupying seven bytes of object code. The generated code loads the selected pointer register with a value that causes execution to begin at the specified target address after the SC/MP's automatic program-counter increment. It uses two LDI instructions together with XPAH and XPAL to construct the required pointer value, then transfers control using XPPC. This is commonly described as loading expression−1, but the SC/MP's 4 KB page structure must be considered when calculating that value.[40][21]

The generated sequence overwrites the contents of the accumulator. The XPPC instruction exchanges the contents of the program counter and a selected pointer register. As a result, the pointer register is loaded with the address of the XPPC instruction while the program counter is loaded with the pointer register's previous contents. Because the SC/MP increments the program counter before instruction fetch, execution resumes from the address obtained by incrementing the value loaded into the program counter, subject to the SC/MP's 4 KB page arithmetic. For example, a subroutine whose first instruction is at 2010 would conventionally be entered by loading a pointer register with 200F before executing XPPC. At a 4 KB page boundary, however, the page field is retained. A routine beginning at 2000 requires the pointer register to contain 2FFF, not 1FFF. A later XPPC using the same pointer register returns execution to the instruction following the call. Because the return pointer is stored in the pointer register itself, nested subroutine calls require software preservation of that register, typically using a software stack.[21][41][5]

Because of this increment-before-fetch behaviour, after reset execution begins at location 0001 rather than 0000. PC-relative displacements are calculated from the program counter value after the instruction bytes have been read rather than from the address of the opcode itself. The same behaviour means that XPPC targets, including interrupt entry addresses held in P3, are conventionally stored as the address immediately preceding the address at which execution is intended to begin, subject to the same page-boundary rule. Because PC-relative addressing cannot reach locations outside the current 4 KB page, programs frequently use XPPC and pointer registers for inter-page subroutine calls, jumps, and data access.[42][43][44]

The SC/MP includes a delay instruction, DLY, a two-byte instruction whose second byte supplies the delay value. It pauses operation for 13 + (2 × AC) + (2 × disp) + (29 × disp) microcycles, counting AC to −1 during the delay.[45][46] The resulting delay ranges from 13 to 131,593 microcycles.[45] One documented use was software-timed serial I/O. The MK14 manual describes serial data-transfer routines in which SIO shifts data through SIN and SOUT, while DLY generates the bit-time delays for the selected baud rate.[47]

The instruction was also useful in shared-bus multiprocessor systems. Hughes and Doone explained that ordinary polling and software delay loops still used the bus because the processor had to keep fetching and executing instructions. During DLY, the SC/MP instead stayed off the bus for the programmed interval, leaving that bus time available to other processors and improving overall system throughput. They also noted that this let several SC/MP processors on the same bus carry out software timing at the same time, avoiding the otherwise unpredictable delays caused by bus conflicts.[48] Osborne and Kane described the limitation of the same approach, noting that although DLY could be treated as a programmable-timer function, the processor could do no other work during the delay and was acting as the timer rather than using a separate timer device.[49]

Implementations

[edit]
NMOS SC/MP-II die (ISP-8A/600)

The original SC/MP was implemented in P Channel MOS (pMOS) and the later SC/MP-II in N Channel MOS (nMOS).[50][51][17]

National Semiconductor produced several related implementations and successors based on the SC/MP architecture:

  • SC/MP (ISP-8A/500), the original pMOS version, operated at up to 1 MHz and required +5 V and -7 V supplies.[52][17]
  • SC/MP-II (ISP-8A/600 or INS8060), the nMOS version, operated at up to 4 MHz and required only a single +5 V supply.[51][17]
  • 70-Series (INS807x), clocked at 4 MHz, included variations with up to 4 KB ROM and optional onboard BASIC (NIBL).[1][2]

The SC/MP included an internal clock oscillator. This was also a feature of contemporary nMOS designs like the 6502, but unusual for a chip originally fabricated in pMOS.[53][54][55][17]

SC/MP-II did not simply run the original design at a higher crystal frequency. National Semiconductor documented that one SC/MP microcycle equals two oscillator periods, whereas one SC/MP-II microcycle equals four oscillator periods, so SC/MP-II needed a higher timing-input frequency for the same internal cycle rate. In practice, this made SC/MP-II about twice as fast as the original SC/MP rather than four times as fast, even though its timing input could run at up to 4 MHz.[56][57][17]

Osborne and Kane described SC/MP-II as functionally equivalent to the original SC/MP and fully compatible in terms of object code and pin configuration, although they noted that minor signal-level conversions were still required for complete signal compatibility.[17] National Semiconductor documentation shows some technical differences in more detail. The original SC/MP documentation names the bus-control signals BREQ, ENIN, and ENOUT. The SC/MP-II documentation names the corresponding active-low signals NBREQ, NENIN, and NENOUT.[30][58]

Second source

[edit]

Signetics was identified by Osborne and Kane as an authorized second source for the SC/MP. They listed National Semiconductor as the prime source and Signetics as the authorized second source, while stating that Signetics had not actually manufactured the processor.[36]

Signetics also published its own documentation for the SC/MP-II. The 1977 Signetics Bipolar/MOS Microprocessor Data Manual listed the ISP-8A/600 "Simple Cost Effective Microprocessor (SC/MP-II)" among its MOS microprocessors and included a Signetics-branded device section for the part.[59]

In the 1982 Signetics MOS Microprocessor Data Manual, the SC/MP-II appeared in application-note material rather than as a standalone product data-sheet entry in the contents. Application note M22, "Interface Techniques for the 2651 PCI", included an SC/MP-II interface example and cited a "Signetics SC/MP II (ISP-8A/600) Microprocessor Specification".[60]

Uses

[edit]

Montgomery Elevator of Moline, Illinois, later acquired by KONE in 1994[61], used the SC/MP in its first[citation needed] microprocessor based elevator, the "MIPROM Hydro elevator-controller system" released in 1975[citation needed]. Montgomery described MIPROM as a "microprocessor elevator logic control" system[62], and a later Otis PC-board catalogue[63] identifies board MTGMP-15783 as a "CPU MIPROM SC/MP II Board". The corresponding P-15783 CPU card is illustrated in the MIPROM I troubleshooting guide[64], and a TK Elevator spare-parts listing identifies P-15783 as a refurbished Montgomery MIPROM CPU board; the board photograph in that listing shows the processor package marked "INS8060N" and "ISP-8A/600N"[65]. The MIPROM I troubleshooting guide also lists CPU card P-15783 as a replacement for P-16782, but the replaced P-16782 is not shown clearly enough to identify the processor used on P-16782.

The SC/MP was used as the basis of a single board microcontroller produced by Science of Cambridge (later Sinclair Research Ltd) called the MK14. This was based on National's own Introkit design, and National offered Sinclair a deal on completed sets which could not be matched by building their own. This allowed the MK14 to sell for the extremely low cost of £39.95.

Doug Neubauer, best known as the author of Star Raiders, had moved to Atari after working at National on a product identified only as a "home computer product".[66] This had progressed to the stage of a wire wrapped prototype before the company killed it.[67]

Instruction set

[edit]

The instruction set consists of one and two-byte instructions. The second byte is often an immediate value or a signed displacement. Most instructions run in 5 to 23 microcycles. Each microcycle takes two external clocks on the original SC/MP.

OpcodeOperandMnemonicMicro
cycles		Description
76543210
00000000—HALT8Assert H-flag at memory/status time.[b][68][69]
00000001—XAE7AC ↔ E
0000001n—CCL SCL5CY/L ← n (Clear/Set carry/link)
0000010n—DINT IEN6IE ← n (Disable/Enable interrupts)
00000110—CSA5AC ← SR
00000111—CAS6Writable SR bits ← AC; read only SA and SB unaffected[16]
00001000—NOP5No operation
00011001—SIO5SOUT ← E0; E0-6 ← E1-7; E7 ← SIN
00011100—SR5AC0-6 ← AC1-7; AC7 ← 0
00011101—SRL5AC0-6 ← AC1-7; AC7 ← CY/L
00011110—RR5AC0-6 ← AC1-7; AC7 ← AC0
00011111—RRL5AC0-6 ← AC1-7; AC7 ← CY/L; CY/L ← AC0
001100PTR—XPAL8AC ↔ PTR0-7
001101PTR—XPAH8AC ↔ PTR8-15
001111PTR—XPPC7PC ↔ PTR
01ALU000—LDE ANE ORE XRE DAE ADE CAE6-11AC ← AC ALU E
10001111delayDLY13+Delay 13 to 131,593 microcycles;[c] AC ← -1
100100PTRdispJMP11PC ← PTR + disp
100101PTRdispJP9-11If AC ≥ 0, PC ← PTR + disp
100110PTRdispJZ9-11If AC = 0, PC ← PTR + disp
100111PTRdispJNZ9-11If AC ≠ 0, PC ← PTR + disp
101010PTRdispILD22AC ← (PTR + disp) ← (PTR + disp) + 1
101110PTRdispDLD22AC ← (PTR + disp) ← (PTR + disp) - 1
11ALU0PTRdispLD AND OR XOR DAD ADD CAD disp(Px) address mode18-23AC ← AC ALU (PTR + effective disp)[d]
110010PTRdispST disp(Px) address mode18(PTR + effective disp) ← AC[d]
11ALU1PTRdispLD AND OR XOR DAD ADD CAD @disp(Px) address mode18-23If effective disp7 = 1, PTR ← PTR + effective disp;
AC ← AC ALU (PTR);
If effective disp7 = 0, PTR ← PTR + effective disp[d][e]
110011PTRdispST @disp(Px) address mode18If effective disp7 = 1, PTR ← PTR + effective disp;
(PTR) ← AC;
If effective disp7 = 0, PTR ← PTR + effective disp[d][e]
11ALU100dataLDI ANI ORI XRI DAI ADI CAI10-15AC ← AC ALU data
76543210OperandMnemonicMicro
cycles		Description
PTR210ALU
PC000LDE LD LDI (AC ← arg)
P1001
P2010ANE AND ANI (AC ← AC ∧ arg)
P3011ORE OR ORI (AC ← AC ∨ arg)
100XRE XOR XRI (AC ← AC ⊻ arg)
101DAE DAD DAI (AC10 ← AC10 + arg10 + CY/L)
110ADE ADD ADI (AC ← AC + arg + CY/L)
111CAE CAD CAI (AC ← AC + ¬arg + CY/L)
PTR210ALU

Example code

[edit]

The following assembler source code is for a subroutine CPYMEM that copies bytes from one location to another. This routine can be used to copy between pages but cannot cross a page. It can be executed from ROM or RAM. If executing from RAM, loop counting could be accelerated with a DLD instruction using a PC-relative counter. This routine uses an unusual @1(P1) addressing mode that is used to auto-index through the memory. Unlike other processors with auto-index such as the 68000, the SC/MP auto-index stride can be larger than the datum size. 

 
 
 
1000
1000 03
1001 01
1002 C5 01
1004 CE 01
1006 C4 FE
1008 70
1009 9C F6
100B 3F

; Copy memory words addressed by P1 to location addressed
; by P2 for a length of up to 255 bytes. Length is passed
; in AC (accumulator). Return address in P3.
        =       X'1000
CPYMEM: SCL                   ; Set carry for upcoming ADD
CPYLP:  XAE                   ; Save count in E
        LD      @1(P1)        ; Get byte to copy, inc P1
        ST      @1(P2)        ; Save it, inc P2
        LDI     -2            ; -2 to AC to decrement
        ADE                   ; E (set carry made it -1)
        JNZ     CPYLP         ; Continue for all bytes
        XPPC    P3            ; Return to caller

Notes

[edit]
  1. ↑ The original SC/MP takes 11 "microcycles" to do an 8-bit add immediate (ADI) with each microcycle requiring two clocks, 22 clocks total (22µS at 1 MHz). Contemporaneous CPUs are faster: The 8080's add immediate (ADI) takes seven clocks (3.5µS at 2 MHz). A 6502 add immediate (ADC) takes two clocks (2µS at 1 MHz).
  2. ↑ H-flag is released on next opcode fetch. Does not halt CPU without external hardware. H-flag may be latched, inverted, and fed into the CONT input to stop CPU under program control.
  3. ↑ Delay is 13 + (2 × AC) + (514 × delay) microcycles
  4. 1 2 3 4 For memory-reference instructions, if disp is 0x80, the contents of register E are substituted for the displacement.
  5. 1 2 Auto-indexing uses the displacement value actually used by the instruction. Normally this is disp. If disp is 0x80, the contents of register E are substituted. A negative value predecrements PTR. A zero or positive value postincrements PTR. See Programming and Assembler Manual 1976, pp. 3–7, 5–5 and Technical Description 1976, pp. 2-19–2-20.

References

[edit]

Citations

[edit]
  1. 1 2 3 "INS8070-Series Microprocessor Family" (PDF). National Semiconductor. October 1980. Retrieved 4 May 2026.
  2. 1 2 3 "70-Series Microprocessor User's Manual" (PDF). National Semiconductor. 1979. Retrieved 4 May 2026.
  3. ↑ "NS INS8070 - SC/MP III". Semiconductor Collection Exhibition Hall (in Japanese). Archived from the original on 18 April 2001. Retrieved 4 May 2026.
  4. 1 2 3 4 Programming and Assembler Manual 1976, p. 3-1.
  5. 1 2 3 Technical Description 1976, p. 2-17.
  6. ↑ Programming and Assembler Manual 1976, p. 5-15.
  7. ↑ Handbook 1977, p. 1-6
  8. ↑ Programming and Assembler Manual 1976, p. 5-13
  9. ↑ Handbook 1977, pp. 1–2, 1–6, 1–10, 1–13
  10. ↑ Programming and Assembler Manual 1976, p. 5-17
  11. ↑ Osborne & Kane 1981, p. 3-3
  12. 1 2 3 4 5 6 Handbook 1977, p. 1-11.
  13. ↑ Programming and Assembler Manual 1976, p. 3-6.
  14. ↑ Handbook 1977, pp. 1-5–1-8.
  15. ↑ Technical Description 1976, p. 2-13.
  16. 1 2 Programming and Assembler Manual 1976, pp. 5–21, 6–11.
  17. 1 2 3 4 5 6 7 8 9 Osborne & Kane 1981, p. 3-3.
  18. ↑ Programming and Assembler Manual 1976, pp. 3-6–3-7.
  19. 1 2 3 Osborne & Kane 1981, p. 3-4.
  20. ↑ Handbook 1977, p. 1-3.
  21. 1 2 3 Handbook 1977, p. 1-5.
  22. ↑ Williamson & Dale 1980, pp. 104–106.
  23. ↑ Programming and Assembler Manual 1976, p. 3-7.
  24. ↑ Programming and Assembler Manual 1976, pp. 5-8–5-9, 5-12–5-13.
  25. 1 2 Programming and Assembler Manual 1976, p. 6-9.
  26. ↑ Osborne & Kane 1981, p. 3-14.
  27. ↑ Programming and Assembler Manual 1976, p. 5-20.
  28. ↑ Osborne & Kane 1981, p. 3-16.
  29. ↑ Handbook 1977, p. C-5.
  30. 1 2 3 4 Technical Description 1976, pp. 2-4–2-6.
  31. 1 2 3 4 INS8060 Datasheet 1978, pp. 10–11.
  32. ↑ Williamson & Dale 1980, pp. 183–187.
  33. ↑ Handbook 1977, p. 1-2.
  34. ↑ Technical Description 1976, p. 2-4.
  35. ↑ Technical Description 1976, pp. 2-5–2-6.
  36. 1 2 Osborne & Kane 1981, p. 3-1.
  37. ↑ Osborne & Kane 1981, pp. 3-8–3-9.
  38. ↑ INS8060 Datasheet 1978, p. 10.
  39. ↑ Programming and Assembler Manual 1976, pp. 5-16–5-17.
  40. ↑ Programming and Assembler Manual 1976, pp. 5-23–5-24.
  41. ↑ Programming and Assembler Manual 1976, pp. 6-1–6-3.
  42. ↑ Technical Description 1976, p. 2-14.
  43. ↑ Williamson & Dale 1980, pp. 64–67.
  44. ↑ Osborne & Kane 1981, pp. 3-14–3-16.
  45. 1 2 Programming and Assembler Manual 1976, p. 5-22.
  46. ↑ Handbook 1977, p. 1-12.
  47. ↑ MK14 Manual, p. 77.
  48. ↑ Hughes & Doone 1977, p. 284.
  49. ↑ Osborne & Kane 1981, pp. 3-1–3-2.
  50. ↑ SC/MP-II Retrofit Kit Users Manual 1977, p. 1.
  51. 1 2 INS8060 Datasheet 1978, p. 1.
  52. ↑ Handbook 1977, p. 1-10.
  53. ↑ Technical Description 1976, p. 2-2.
  54. ↑ Handbook 1977, pp. 1–1, A-1.
  55. ↑ MCS6500 Hardware Manual 1976, p. 41.
  56. ↑ Handbook 1977, p. E-1.
  57. ↑ INS8060 Datasheet 1978, p. 7.
  58. ↑ INS8060 Datasheet 1978, pp. 5, 10–11.
  59. ↑ Signetics 1977, contents p. 5; SC/MP II section pp. 146–162.
  60. ↑ Signetics 1982, contents p. ii; App Note M22, pp. 6-6–6-7.
  61. ↑ "History". KONE Corporation. Retrieved 5 May 2026.
  62. ↑ "Miprom: Microprocessor Elevator Logic Control for the Mass Elevator Market" (PDF) (Brochure). Montgomery Elevator Company. pp. 1–3. Retrieved 5 May 2026 – via KONE Spares.
  63. ↑ Otis PC Board Catalog (PDF). Otis Elevator Company. November 2010. p. 73. Retrieved 5 May 2026.
  64. ↑ MIPROM I Troubleshooting Guide. Montgomery Elevator Company. October 1990. pp. 14, 69. 61111-753. Retrieved 5 May 2026.
  65. ↑ "Refurbished MIPROM CPU Board Montgomery P-15783". TKE Spare Parts. TK Elevator Manufacturing, Inc. Retrieved 5 May 2026.
  66. ↑ Fleming, Jeffrey (September 20, 2007). "Video Games' First Space Opera: Exploring Atari's Star Raiders". Archived from the original on February 27, 2008. Retrieved May 28, 2024.
  67. ↑ Neubauer, Doug. "The Atari Years".
  68. ↑ Technical Description 1976, Appendix A, table A-3, p. A-11.
  69. ↑ Programming and Assembler Manual 1976, p. 5-19.

Bibliography

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