Propagation delay

Propagation delay is the time duration taken for a signal to reach its destination through a medium, such as an electromagnetic field, a conductive wire, a gas, a fluid, or a solid body.

Physics

• An electromagnetic wave travelling through a medium has a propagation delay determined by the speed of light in that specific medium, or approximately 1 nanosecond per 29.98 centimetres (11.80 in) in a vacuum.
• An electrical signal travelling through a copper wire has a propagation delay of approximately 1 nanosecond per 15 centimetres (5.9 in).

See also radio propagation, velocity factor, signal velocity, and mechanical wave.

Electronics

Propagation delay timing diagram of a NOT gate.

A full adder has an overall gate delay of 3 logic gates from inputs A and B to the carry output C_out (shown in red).

Logic gates have a gate delay ranging from picoseconds to several nanoseconds, depending on the manufacturing technology. It is defined as the time interval between the moment an input transition reaches 50% of its logic level and the moment the corresponding output reaches 50% of its final logic level. Because transition speeds may differ between rising and falling edges, separate delays are specified for high-to-low (t_PHL or t_f) and low-to-high (t_PLH or t_r) transitions.

Reducing gate delays allows digital circuits to operate at higher clock frequencies, improving overall system performance. To determine the total propagation delay of a combinational logic circuit, one must identify the critical path—the longest sequence of propagation delays from any input to any output—and sum the individual gate delays along that path.

The principle of logical effort utilizes propagation delays to evaluate and compare different circuit topologies implementing the same boolean logic. Variations in propagation delays across parallel logic paths are the primary cause of glitches and dynamic hazards in asynchronous circuits due to race conditions.

• Temperature: Propagation delay changes with operating temperature. In metallic interconnects, higher temperatures increase electrical resistance, increasing delay. In semiconductors, higher temperatures generally slow down carrier mobility, increasing delay. However, in advanced sub-micron devices (such as FinFETs), rising temperatures can decrease gate delay due to Inverse Temperature Dependence (ITD).
• Supply Voltage: Increasing the supply voltage ($V_{DD}$) increases the drive current ($I_{DS}$) of MOSFET transistors, which generally decreases propagation delay and makes the circuit faster. Conversely, lowering the supply voltage increases propagation delay, a key trade-off in dynamic voltage scaling (DVS) power-saving techniques.
• Output Load Capacitance: Connecting additional logic gate inputs (fan-out) or long PCB traces to an output increases its load capacitance, which increases the time required to charge or discharge the node.

These physical factors dictate the propagation delay through the RC time constant equation:

$\tau =R\times C$

Where $R$ is the equivalent resistance of the driving transistor (and interconnect) and $C$ is the total load capacitance. Any increase in load capacitance ($C$) or heat-induced resistance ($R$) directly scales the propagation delay $\tau$.

Networking

In computer networking, propagation delay is the time required for the first bit (head) of a signal to travel from the sender to the receiver across a physical link. It is calculated as the ratio between the physical distance of the link and the propagation speed over the specific transmission medium:

${\text{Propagation Delay}}={\frac {d}{s}}$

Where $d$ is the link distance and $s$ is the wave propagation speed.

• In wireless communications, $s=c$ (the speed of light in a vacuum, $\approx 3\times 10^{8}{\text{ m/s}}$).
• In copper wire or optical fiber, the speed $s$ typically ranges from $0.59c$ to $0.77c$ depending on the dielectric constant of the material.

In modern integrated circuit (IC) design, propagation delay in physical wiring is often a major bottleneck preventing faster clock speeds, a phenomenon known as the interconnect bottleneck.

See also

• Contamination delay
• Critical path method
• Latency (engineering)
• Time of flight
• Transmission delay