IBM Elastic Interface
Elastic interface buses, abbreviated as EI bus connections, can be generalized as bus connections which are high speed interfaces that send clock signals with data.
Description
[edit]The data bits that are sent through EI bus connections are aligned to the clock so that they latch to the data at the high speeds. EI bus connections require that the net topology and timing characteristics for each net on the bus are at least similar to each other in order to make lining up the edges of the data to the clock signals possible. In this environment, re-working connections in the connection module was not easily possible because all nets needed to have similar topology and timing characteristics. This increased the difficulty of a re-work solution or made it impossible and increased the modules that needed to be scrapped as unusable.
Repair
[edit]Elastic Interface repair involves a spare wire that is built into the bus interface in the connection module that has the same topology and characteristics of the rest of the nets in the bus. It includes hardware that is able to switch from the bad net in the interface to the spare net (as of now, this operation must be supported by the original manufacturer of the EI bus connector). The connection module is tested at several different process corners such as low and high temperature and low and high voltages. When a net on the interface is known to be bad, the spare net is used on the bus for testing and the bad net is not tested. When the bus does not have a defect, the spare net is tested with the functional nets. In the original design specification for the EI spare, the wire was driven with a constant zero when not used.[1]
Applications
[edit]See also
[edit]References
[edit]- ↑ "Peer to Patent activity on US Pre-Grant Patent Publication Number: US20080082878 'System and method to support use of bus spare wires in connection modules'" Archived 2008-08-04 at the Wayback Machine July 20, 2008
- ↑ "Mai Logic, Inc. Licenses IBM(R)'S Elastic Interface Technology For Its Articia Chipset Family and Teron Series Systems in Support Of IBM(R)'S Powerpc(TM) 970 Microprocessor Family}. Press Release, 12/22/03
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Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.  Category | |
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